PowerPC (PPC)

The PowerPC is a RISC microprocessor designed to meet a standard which was designed by Motorola, IBM, and Apple Computer (the PowerPC Alliance). The PowerPC standard specifies a common instruction set architecture (ISA), allowing anyone to design and fabricate PowerPC processors, which will run the same code. The PowerPC architecture is based on the IBM POWER architecture, used in IBM's RS/6000 workstations. Currently IBM and Motorola are working on PowerPC chips.

The PowerPC standard specifies both 32 bit and 64 bit data paths. Early implementations will be 32 bit; future higher-performance implementations will be 64 bit (e.g. PowerPC 601). A PowerPC has 32 integer registers (32- or 64 bit) and 32 floating-point (IEEE standard 64 bit) floating-point registers.

The POWER CPU chip and PowerPC have a (large) common core, but both have instructions that the other doesn't. The PowerPC offers the following features that POWER does not:

• Support for running in little-endian mode.
• Addition of single precision floating-point operations.
• Control of branch prediction direction.
• A hardware coherency model (not in Book I).
• Some other floating-point instructions (some optional).
• The real time clock (upper and lower) was replaced with the time base registers (upper and lower), which don't count in sec/ns (the decrementer also changed).
• 64 bit instruction operands, registers, etc. (in 64 bit processors).

• Read the PowerPC FAQ from Motorola.
• Or read the PowerPC FAQ text-file version right here (quicker).

RISC

Reduced Instruction Set Computer
The PowerPC CPU is RISC based instead of the PC's and Amiga's CISC based CPU. This type of processors are also used in the PowerMac, but at a much higher price. It's a processor with designbased on the rapid execution of a sequence of simple instructions rather than on the provision of a large variety of complex instructions (as in a Complex Instruction Set Computer).

Features which are generally found in RISC designs are uniform instruction encoding (e.g. the op-code is always in the same bit positions in each instruction which is always one word long), which allows faster decoding; a homogenous register set, allowing any register to be used in any context and simplifying compiler design; and simple addressing modes with more complex modes replaced by sequences of simple arithmetic instructions.

RISC technology has a much brighter future than CISC. It's faster, and cost-effective!