Performance optimizations, implementation, and verification
of the SGI Challenge multiprocessor
Mike Galles and Eric Williams
Silicon Graphics Computer Systems
Abstract
This paper presents the architecture, implementation,
and performance results for the SGI Challenge symmetric
multiprocessor system. Novel aspects of the architecture will
be highlighted, as well as key design trade-offs targeted at
increasing performance and reducing complexity. Multiprocessor
design verification techniques and their impact will also be
presented. The SGI Challenge system architecture provides a
high-bandwidth, low-latency cache-coherent interconnect for several
high performance processors, I/O busses, and a scalable memory system.
Hardware cache coherence mechanisms maintain a consistent view of shared
memory for all processors, with no software overhead and minimal impact
on processor performance. HDL simulation with random, self checking vector
generation and a lightweight operating system on full processor models
contributed to a concept to customer shipment cycle of 26 months.
Introduction
The Silicon Graphics Challenge line of symmetric multiprocessing
computers is designed to provide engineers and scientists with a
powerful set of computational, de sign, and visualization tools at
aggressive price performance levels. Scalability and balance across
processor, memory, and I/O subsystems also makes these computers
attractive to a wide range of high performance computing applications,
from the creation of special effects for the entertainment industry to
database management in the commercial sector. This paper begins with
an overview of the system parameters and configurations, then moves
directly into presentation of the coherence protocol, latency reduction
techniques, and bus efficiency mechanisms, with emphasis on performance
impact. The I/O bus and subsystem is later described, followed up by a
discussion of effective design verification techniques used to reduce the
overall product cycle time. Finally, performance results are presented and
summarized.
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